System Centering Solutions's Press And Articles

Method, apparatus, and computer program product for facilitating marketing between businesses

April 2, 2015

A method, apparatus and computer program product are provided for facilitating a marketing interlock between businesses. Two or more businesses may enter into a co-marketing campaign in which a sponsoring entity funds an advertisement of a sponsored entity on a third party advertising system, such as a search engine. Marketing content of the sponsoring entity is inserted on the website of the sponsored entity. Traffic originating on the third party advertising system may therefore first be driven to the sponsored entity's website, and subsequently to the sponsoring entity's website, thereby achieving a mutually beneficial co-marketing relationship. Marketing relationships among complimentary businesses based on provided service and location may also be facilitated according to the methods provided (Full Patent Here).

Empirical results from the transformation of a large commercial technical computing environment

October 15, 2009

Technical computing has unique requirements which are exemplified by factors such as: an extreme focus on run-time performance, a high degree of responsiveness to the customer base, a continued focus on innovation, concurrent support on multiple computing platforms and most importantly, a very limited set of deep subject matter experts who have the skills to build the solution. Exacerbating the above issues is the fact that the field has traditionally seen a great deal of mergers and acquisition activity which leads quickly to an accumulation of disjoint software development systems. This paper describes a detailed case study built within a leading technical computing company which achieved significant success by focusing relentlessly on enhancing the productivity of the individual developer. The work was driven by the author as the general manager of the organization, and measured results of the transformation will be presented in this paper.Full Article in Proceedings of the 2009...

Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques

May 2, 2006

Disclosed is a full-chip level verification methodology that combines static timing analysis techniques with dynamic event-driven simulation. The specification discloses a capability to partition a multiple-clock design into various clock domains and surrounding asynchronous regions automatically and to determine the timing of the design on an instance by instance basis. Static timing analysis techniques can be leveraged to verify the synchronous cores of each clock domain. The asynchronous regions of the design and the interaction between synchronous cores of the clock domains are validated using detailed dynamic event-driven simulation without the burden of carrying the interior timing attributes of the synchronous cores that have already been verified (Full Patent Here).

Method and apparatus for critical and false path verification

March 30, 2004

A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, but can be a simplified gate level representation because the verification process is only concerned with the logical behavior, not the actual structure. This allows the simulation to execute more quickly. Since the conditions are only captured between register elements, it can be formally proved whether or not the path can be exercised. If no register value can activate the path, then the analysis is done. Otherwise, a simulation is performed to determine whether the register values required to active the condition actually occur. If the Boolean condition can be satisfied, the simulation is performed on the sequential logic to justify those values. If the satisfiability engine fails...

Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state

November 18, 2003

A computer system includes an external unit governing a cache which generates a set-dirty request as a function of a coherence state of a block in the cache to be modified. The external unit modifies the block of the cache only if an acknowledgment granting permission is received from a memory management system responsive to the set-dirty request. The memory management system receives the set-dirty request, determines the acknowledgment based on contents of the plurality of caches and the main memory according to a cache protocol and sends the acknowledgment to the external unit in response to the set-dirty request. The acknowledgment will either grant permission or deny permission to set the block to the dirty state (Full Patent Here).

Method and apparatus for performing speculative memory fills into a microprocessor

December 10, 2002

According to the present invention a cache within a multiprocessor system is speculatively filled. To speculatively fill a designated cache, the present invention first determines an address which identifies information located in a main memory. The address may also identify one or more other versions of the information located in one or more caches. The process of filling the designated cache with the information is started by locating the information in the main memory and locating other versions of the information identified by the address in the caches. The validity of the information located in the main memory is determined after locating the other versions of the information. The process of filling the designated cache with the information located in the main memory is initiated before determining the validity of the information located in main memory. Thus, the memory reference is speculative (Full Patent Here).

Method and apparatus for delaying the execution of dependent loads

October 8, 2002

Load/ store execution order violations in an out-of-order processor are reduced by determining whether a source address of a load instruction is the same as a destination address of a store instruction on which execution the load instruction depends. If they are the same, then execution of the load instruction is delayed until execution of the store instruction. In an system where virtual registers are mapped to a physical register, the physical registers mapped by the store and load instructions are compared. A table has entries corresponding to instructions in an instruction queue. In each table entry corresponding to a store instruction, the store instruction's destination address offset and physical register reference are saved. A load instruction's source address offset and physical reference are compared with each of the table entries corresponding to store instructions to determine whether a dependency exists. Furthermore, a matrix also has row entries corresponding to...

Methods and apparatus for minimizing the impact of excessive instruction retrieval

September 3, 2002

A technique controls memory access requests. The technique involves acquiring a first series of requests including a prefetch request for performing a prefetch operation that prefetches a first set of instructions from a memory, and adding a first entry in a request queue in response to the prefetch request. The first entry identifies the prefetch operation. The technique further involves attempting to retrieve a second set of instructions from a cache to create a cache miss, and generating, in response to the cache miss, a second series of requests including a fetch request for performing a fetch operation that fetches the second set of instructions from the memory to satisfy the cache miss. The technique further involves acquiring the second series of requests that includes the fetch request, and adding a second entry in the request queue in response to the fetch request. The second entry identifies the fetch operation. The technique further involves invalidating the first entry...

Method and apparatus for optimizing bcache tag performance by inferring bcache tag state from internal processor state

June 4, 2002

An architecture which splits primary and secondary cache memory buses and maintains cache hierarchy consistency without performing an explicit invalidation of the secondary cache tag. Two explicit rules are used to determine the status of a block read from the primary cache. In particular, if any memory reference subset matches a block in the primary cache, the associated secondary cache block is ignored. Secondly, if any memory reference subset matches a block in the miss address file, the associated secondary cache block is ignored. Therefore, any further references which subset match the first reference are not allowed to proceed until the fill back to main memory has been completed and the associated miss address file entry has been retired. This ensures that no agent in the host processor or an external agent can illegally use the stale secondary cache data (Full Patent Here).

Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external system

May 28, 2002

A multiprocessor system includes a plurality of processors, each processor having one or more caches local to the processor, and a memory controller connectable to the plurality of processors and a main memory. The memory controller manages the caches and the main memory of the multiprocessor system. A processor of the multiprocessor system is configurable to evict from its cache a block of data. The selected block may have a clean coherence state or a dirty coherence state. The processor communicates a notify signal indicating eviction of the selected block to the memory controller. In addition to sending a write victim notify signal if the selected block has a dirty coherence state, the processor sends a clean victim notify signal if the selected block has a clean coherence state (Full Patent Here).

Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commands

February 19, 2002

A memory management system couples processors to each other and to a main memory. Each processor may have one or more associated caches local to that processor. A system port of the memory management system receives a request from a source processor of the processors to access a block of data from the main memory. A memory manager of the memory management system then converts the request into a probe command having a data movement part identifying a condition for movement of the block out of a cache of a target processor and a next coherence state part indicating a next state of the block in the cache of the target processor (Full Patent Here).

Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commands

November 6, 2001

A computing apparatus connectable to a cache and a memory, includes a system port configured to receive an atomic probe command or a system data control response command having an address part identifying data stored in the cache which is associated with data stored in the memory and a next coherence state part indicating a next state of the data in the cache. The computing apparatus further includes an execution unit configured to execute the command to change the state of the data stored in the cache according to the next coherence state part of the command (Full Patent Here).

Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filtering

September 25, 2001

A processor of a multiprocessor system is configured to transmit a full probe to a cache associated with the processor to transfer data from the stored data of the cache. The data corresponding to the full probe is transferred during a time period. A first tag-only probe is also transmitted to the cache during the same time period to determine if the data corresponding to the tag-only probe is part of the stored data stored in the cache. A stream of probes accesses the cache in two stages. The cache is composed of a tag structure and a data structure. In the first stage, a probe is designated a tag-only probe and accesses the tag structure, but not the data structure, to determine tag information indicating a hit or a miss. In the second stage, if the probe returns tag information indicating a cache hit the probe is designated to be a full probe and accesses the data structure of the cache. If the probe returns tag information indicating a cache miss the probe does not proceed to...

Method and apparatus for a dedicated physically indexed copy of the data cache tag arrays

June 26, 2001

A data caching system and method includes a data store for caching data from a main memory, a primary tag array for holding tags associated with data cached in the data store, and a duplicate tag array which holds copies of the tags held in the primary tag array. The duplicate tag array is accessible by functions, such as external memory cache probes, such that the primary tag remains available to the processor core. An address translator maps virtual page addresses to physical page address. In order to allow a data caching system which is larger than a page size, a portion of the virtual page address is used to index the tag arrays and data store. However, because of the virtual to physical mapping, the data may reside in any of a number of physical locations. During an internally-generated memory access, the virtual address is used to look up the cache. If there is a miss, other combinations of values are substituted for the virtual bits of the tag array index. For external...

Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/ subset processing

June 26, 2001

A data caching system comprises a hashing function, a data store, a tag array, a page translator, a comparator and a duplicate tag array. The hashing function combines an index portion of a virtual address with a virtual page portion of the virtual address to form a cache index. The data store comprises a plurality of data blocks for holding data. The tag array comprises a plurality of tag entries corresponding to the data blocks, and both the data store and tag array are addressed with the cache index. The tag array provides a plurality of physical address tags corresponding to physical addresses of data resident within corresponding data blocks in the data store addressed by the cache index. The page translator translates a tag portion of the virtual address to a corresponding physical address tag. The comparator verifies a match between the physical address tag from the page translator and the plurality of physical address tags from the tag array, a match indicating that data...

Distributed data dependency stall mechanism

June 19, 2001

A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance (Full Patent Here).

Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements

March 6, 2001

A computing apparatus has a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size. An address bus of the computing apparatus is configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size. The address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N (Full Patent Here).

Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol

October 31, 2000

A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag or local lock address registers for each individual locked address. Integrity of locked data is accomplished by insuring that load-locked and store-conditional instructions are processed in order, that no internal agents can evict blocks from a local cache as a side effect as their processing, that external agents update the context of cache memories first using invalidating probe commands, and that only non-speculative instructions are permitted to generate external commands (Full Patent Here).

Distributed data dependency stall mechanism

July 4, 2000

A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory subsystem, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance (Full Patent Here).

Determining hardware complexity of software operations

March 7, 2000

A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle (Full Patent Here).

Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times

July 13, 1999

Use of an internal processor data bus is maximized in a system where external transactions may occur at a rate which is fractionally slower than the rate of the internal transactions. The technique inserts a selectable delay element in the signal path during an external operation such as a cache fill operation. The one cycle delay provides a time slot in which an internal operation, such as a load from an internal cache, may be performed. This technique therefore permits full use of the time slots on the internal data bus. It can, for, example, allow load operations to begin at a much earlier time than would otherwise be possible in architectures where fill operations can consume multiple bus time slots (Full Patent Here).

Hardware extraction technique for programmable reduced instruction set computers

October 6, 1998

A new class of purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle (Full Patent Here).

Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents

December 9, 1997

A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle (Full Patent Here).

Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation

December 2, 1997

Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to charge sharing, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. A three-state version of simulation code is generated for the circuit design, the three states corresponding to states 0, 1, or X, where X represents an undefined state. A preanalysis was performed of the three-state version and phase waveforms are stored each representing values occurring at a node of the code. For each phase of a module for which no event-based evaluation need be performed, an appropriate response to an event occurring with respect to the module of the three-state version is determined and stored. A two-state version of simulation code for the circuit design, the two states...

Formal implementation verification of the bus interface unit for the Alpha 21264 microprocessor

October 12, 1997

In this paper we present our method of formal verification of the transistor implementation of the Bus Interface Unit (BIU) of the Alpha 21264 microprocessor. We compare the logical description compiled from the Register Transfer Level (RTL) against that extracted from the custom-designed transistor-level schematics. BOVE, our BDD-based verification tool, does not require latch-to-latch correspondence, thus allowing the RTL to be more stable during the design process and giving the schematic designers freedom to implement race and timing optimizations. A unique "retiming" comparison algorithm efficiently compares partitions that include multiple pipeline stages, retiming optimizations and precharge logic. BOVE also verifies small finite-state machines that have different state encodings in the RTL and schematic.Full Article in  Proceedings., 1997 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1997. ICCD'97.

The Alpha 21264: a 500 MHz out-of-order execution microprocessor

February 23, 1997

The paper describes the internal organization of the 21264, a 500 MHz, out of order, quad fetch, six way issue microprocessor. The aggressive cycle time of the 21264 in combination with many architectural innovations, such as out of order and speculative execution, enable this microprocessor to deliver an estimated 30 SpecInt95 and 50 SpecFp95 performance. In addition, the 21264 can sustain 5+ Gigabytes/sec of bandwidth to an L2 cache and 3+ Gigabytes/sec to memory for high performance on memory-intensive applications.Full Article in Compcon'97. Proceedings, IEEE

Simulation of circuits

August 27, 1996

Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. The simulation code is preanalyzed and phase waveforms are stored each representing values occurring at a node in successive phases. Based on the preanalysis, modules are categorized in a first category, for which an event-based evaluation is to be performed in each phase of the simulation, and a second category for which no event-based evaluation need be performed in at least one but not all phases. For each phase of a second category module, an appropriate response to an event occurring with respect to the module is determined. A data structure is then included in the simulation code, having an entry for each module of the code for controlling the phases in...

High capacity netlist comparison

October 31, 1995

A method for determining whether multiple representations of a design of a circuit are consistent with each other, where the circuit includes multiple devices with channels for conducting electrical current. Each representations includes a list of device elements that describe the devices and node elements that describe the nodes which interconnect the devices. The method includes modifying each of the lists by: (1) analyzing the device elements and the node elements to identify at least one channel connected region of said circuit (where a channel connected region includes the subset of the devices that have channels interconnected by a subset of the nodes), (2) defining, for each channel connected region, a channel connected region element that describes the subset of the devices and the subset of the nodes in the region, and (3) replacing the device elements of each subset of devices and the node elements of each subset of nodes in the lists with the channel connected...

A high-performance microarchitecture with hardware-programmable functional units

November 30, 1994

This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive data path operations. In this paper, we concentrate on the micro architectural design of the simplest form of PRISC—a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming...

PRISC software acceleration techniques

October 10, 1994

Programmable reduced instruction set computers (PRISC) are a new class of computers which can offer a programmable functional unit (PFU) in the context of a RISC datapath. PRISC create application-specific instructions to accelerate the performance for a particular application. Our previous work has demonstrated that peephole optimizations in a compiler can utilize PFU resources to accelerate the performance of general purpose programs. However these compiler optimizations are limited by the structure of the input source code. This work generalizes on our previous work, and demonstrates that the performance of general abstract data types such as short-set vectors, hash tables, and finite state machines is significantly accelerated (250%-500%) by using PFU resources. Thus, a wide variety of end-user applications can be specifically designed to use PFU resources to accelerate performance. Results from applications in the domain of computer-aided design (CAD) are presented to...

PRISC: Programmable reduced instruction set computers

January 1, 1994

This thesis introduces Programmable Reduced Instruction Set Computers (PRISC) as a new class of general-purpose computers. PRISC use RISC techniques as a base, but in addition to the conventional RISC instruction resources, PRISC offer hardware programmable resources which can be configured based on the needs of a particular application. This thesis presents the architecture, operating system, and programming language compilation techniques which are needed to successfully build PRISC. Performance results are provided for the simplest form of PRISC -- a RISC microprocessor with a set of programmable functional units consisting of only combinational functions. Results for the SPECint92 benchmark suite indicate that an augmented compiler can provide a performance improvement of 22% over the underlying RISC computer with a hardware area investment less than that needed for a 2 kilobyte SRAM. In addition, active manipulation of the source code leads to significantly higher local...

Clock suppression techniques for synchronous circuits

October 1, 1993

A clock suppression based technique that takes advantage of the higher abstraction level provided by synchronous design techniques to improve logic simulation performance was given by the authors (see Proc. IEEE Int. Conf. on Comput. Aided Des. Integr. Circuit Syst., pp.62-65, 1990). Here, the authors elaborate on those techniques and present extensions that can offer an average performance increase of over 5* and a peak performance increase of over 10* that of a conventional logic simulator. The viability of the approach is shown by presenting results from switch-level simulations of large industrial examples. It is shown that because clock suppression based techniques are CPU-bound, they can take advantage of the recent explosive growth of CPU performance.Full Article in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

HCNC: High capacity netlist compare

September 5, 1993

The author describes HCNC (High Capacity Netlist Compare), a technique for netlist comparison that uses the natural hierarchy of the transistor circuit to significantly increase the capacity of traditional netlist comparison algorithms. Since the natural hierarchy of the circuit is used, HCNC does not require hierarchical information from the user. HCNC also has some desirable properties for error recovery. Results from the network comparison of several large industrial circuits shall show the viability of this algorithm.Full Article in Proceedings of the IEEE 1993, Custom Integrated Circuits Conference, 1993

Automatic detection of MOS synchronizers for timing verification

November 11, 1991

Static timing verifiers need to know at which points data are synchronized with clocks in a circuit. Typically, this happens at latches and in clock qualification gates. However, in a general, full-custom VLSI methodology, the 'latch-equivalents' are far more varied and difficult to detect reliably. The authors define these synchronization points, and present provably robust algorithms to locate them in a very general class of MOS networks, including arbitrary pass gates. The algorithms have been applied to a variety of full-custom CPUs of up to 500 K devices, and have been found to work extremely reliably and quite fast.Full Article in IEEE International Conference on Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991

Concurrent min-max simulation

February 25, 1991

Parametric process variations, which are inherent in the manufacture of complex digital circuits, can cause variations in the timing characteristics of a digital device. These device timing variations can cause catastrophic failures to the intended logical operation of the whole design. Min-Max Timing Simulation is a simulation technique which is well suited to verify that a given design functions correctly, even under the influence of parametric process variations. Unfortunately, in the past, Min-Max Timing Simulation has been very expensive in simulation CPU time and in the amount of memory consumed. We present a technique, Concurrent Min-Max Simulation (CMMS), which employs the techniques developed in Concurrent Fault Simulation, to elegantly solve the Min-Max Timing simulation problem.Full Article in Proceedings of the conference on European design automation

Exploitation of periodicity in logic simulation of synchronous circuits

November 11, 1990

An overwhelming majority of logic designers use synchronous logic design techniques to manage the complexity of their designs and rely on logic simulation techniques for design verification. Yet, logic simulators do not take advantage of the higher abstraction level provided by synchronous logic design techniques to improve their performance. A general technique is presented which takes advantage of the high degree of periodicity common in synchronous logic designs. It is shown that a performance improvement of at least 200% occurs when these techniques are applied within the COSMOS. simulation system to simulate large digital systems.Full Article in IEEE International Conference on Computer-Aided Design, 1990. ICCAD-90. Digest of Technical Papers., 1990

A global feedback detection algorithm for VLSI circuits

September 17, 1990

A global feedback detection algorithm for VLSI circuits is presented. It can identify all the global feedback loops within reasonable computational time. The overall algorithm is as follows: First, all the strongly connected components (SCC) are found using a modified version of the Tarjan algorithm which can handle circuits with flip-flops and latches. Second, each SCC recursively cuts the loops based on heuristic criteria to reduce computation time and space until all loops inside this SCC are out. The modified Tarjan algorithm for finding SCCs in circuits consisting of functional primitive elements such as flip-flops and latches is described. A recursive loop-cutting algorithm for strongly connected components is presented, and a top-level partitioning scheme to reduce memory requirements and computation time for finding global feedback loops is proposed.Full Article in ICCD'90 Proceedings, 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors,...

An interactive sequential test pattern generation system

August 29, 1989

The authors present ITPG (Interactive Test Pattern Generator), an automatic test pattern generation tool which produces high fault coverage for complex sequential circuits. The tool is more successful than previous attempts at sequential test generation because of the innovative heuristics and high-level sequential primitives used in the system. Old heuristics, such as controllability and observability, have been extended to the sequential world, and a new heuristic, grouping, has been added to accelerate sequential test pattern generation. In addition, the tool allows the designer to influence the test generation process, thus resulting in the 'interactive' nature of the tool. Results from real industrial VLSI circuits show the effectiveness of this tool.Full Article in International Test Conference Proceedings, Meeting the Tests of Time 1989

A statistical design rule developer

October 1, 1986

In this paper, a general methodology for design rule development and the CAD tool which implements this methodology, Statistical Design Rule Developer (STRUDEL), are presented. The focus of the proposed approach is the concept of a statistical design rule, which is defined as a geometric design rule with an associated probability of failure. Global lateral variations obtained from FABRICS, and local spot defects obtained from measurements are taken into account when calculating the probability of failure. A failure model which accounts for catastrophic faults has been enhanced to include some parametric faults. STRUDEL can be used as a guide to generate layout design rules and may be extended to a wide range of applications including coarse yield estimation during design rules check.Full Article in IEEE transactions on computer-aided design of integrated circuits and systems