An architecture which splits primary and secondary cache memory buses and maintains cache hierarchy consistency without performing an explicit invalidation of the secondary cache tag. Two explicit rules are used to determine the status of a block read from the primary cache. In particular, if any memory reference subset matches a block in the primary cache, the associated secondary cache block is ignored. Secondly, if any memory reference subset matches a block in the miss address file, the associated secondary cache block is ignored. Therefore, any further references which subset match the first reference are not allowed to proceed until the fill back to main memory has been completed and the associated miss address file entry has been retired. This ensures that no agent in the host processor or an external agent can illegally use the stale secondary cache data (Full Patent Here).