Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty state

Posted at 10:00 am on 11/18/2003 by Dr. Rahul Razdan

A computer system includes an external unit governing a cache which generates a set-dirty request as a function of a coherence state of a block in the cache to be modified. The external unit modifies the block of the cache only if an acknowledgment granting permission is received from a memory management system responsive to the set-dirty request. The memory management system receives the set-dirty request, determines the acknowledgment based on contents of the plurality of caches and the main memory according to a cache protocol and sends the acknowledgment to the external unit in response to the set-dirty request. The acknowledgment will either grant permission or deny permission to set the block to the dirty state (Full Patent Here).

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